Conventional microcontrollers typically operate at frequencies that are lower than the highest clock frequencies that are available within the device. A slower clock frequency is typically used to reduce power consumption by a central processing unit (CPU) of a microcontroller. Usually within a microcontroller there is a very fast master clock signal (e.g., 100 megahertz (MHz)) that is divided down to slower rates and distributed throughout its subunits. For example, in a typical microcontroller, the CPU may operate at only 12 MHz in order to reduce its power consumption. Note that when an interrupt is received by the CPU of the microcontroller, the CPU must complete its current task and then execute an interrupt service routine (ISR) corresponding to the received interrupt. Unfortunately, the slower clocked CPU takes longer to respond to an interrupt request. Therefore, by slowing the CPU's clock to help reduce power consumption, interrupt latency of the microcontroller is increased. It is noted that the interrupt latency is the time it takes the CPU to start executing the ISR once the interrupt is signaled. In certain applications that timing can be critical. One conventional technique for keeping that latency within an acceptable limit is to constantly operate the CPU at a higher clock frequency. However, the disadvantage of this conventional technique is an increase in power consumption by the CPU.
As such, it is desirable to address one or more of the above issues.